The subject system and method are generally directed to removing redundancy in a set of timing models of a circuit design. In particular, although not exclusively, a set of timing views for a circuit design is organized into a set of compatibility groups, based on whether process corners are shared between the timing views, and one extracted timing model is generated for each compatibility group.
With the increase in the size of circuit designs, divide-and-conquer methodologies, executed using hierarchical design implementation and sign-off, have become the preferred design approach. One of the extensively employed methodologies for hierarchical design implementation is based on the Extracted Timing Model (ETM). An ETM encapsulates the timing information of the interface-paths of a given block, often although not necessarily in Synopsys Liberty Format (.lib format). The ETMs of different blocks of a design are extracted and plugged-in at the top-level for performing top-level timing analysis. The ETM-based methodology is widely used both for design implementation and timing sign-off.
However, at advanced technology nodes the process-induced variations tend to have large impact on the electrical characteristics of switching devices, as well as on the behavior of interconnects. As a result, Process-Voltage-Temperature (PVT) variations at the gate and interconnect levels, as well as the number of functional and test modes (that is, analysis modes), have dramatically increased the number of requisite “timing views” to cover all mode-corner combinations. In general, for a given block the interface-level timing for different timing views are different. Therefore, for a given design, ETMs are typically extracted separately for each different timing view for each different block.
The runtime of generating ETMs for all the views using the above methodology is proportional to the number of timing views. With the number of timing views reaching into the hundreds in advanced processes, this methodology becomes inefficient and creates a significant hit in timing closure flows. Additionally, computationally intensive operations arising due to advanced delay models, waveform computation/propagation, SI-effects, glitch-analysis, etc. make the runtime of model-extraction for a single timing view significantly high. As a result, generating ETMs multiple times using the above methodology becomes unacceptable for advanced process designs. Specific issues include:
a. For each timing view, a new timing graph needs to be built. This incurs a heavy runtime penalty.
b. For each timing view, interface paths are enumerated separately, even though much of the information, such as information regarding the topology of the design, might be shared among different timing views.
c. For each timing view, delay calculations for various stages are done separately, even though many of the computations are similar for different timing views, and may be shared.
d. Validating and handing-off with so many ETMs is unduly manual, error prone, and problematic. The user needs to keep track of the corners, modes and associated view for each generated ETM and needs to appropriately plug them in for top-level timing analysis.
Therefore, there is a need for a robust, efficient, automated yet reliable ETM-based method and system for multiple-mode multiple-corner (MMMC) designs.